Increasing pin counts, as well as faster circuit speeds, have compounded the need for reliable ESD protection in integrated circuits (ICs). Input/output signals to a complimentary metal oxide semiconductor (CMOS) circuit are typically fed to input/output pads which are connected to the gates of metal oxide semiconductor (MOS) transistors. If high static discharge voltage is accidently applied to any of the input/output pins of an IC, the input/output transistor's gate insulator and the contacts between the pad and the underlying active area are vulnerable to damage if adequate ESD protection is not present. Therefore, all pins of MOS ICs must be ESD protected to prevent any harmful static discharge voltages from damaging the IC.
Four main types of ESD protection circuits have been implemented in IC design which are intended to provide a current path to ground to absorb the high static discharge voltage. These four main ESD protection circuits include: 1) diode breakdown, 2) node-to-node punchthrough, 3) gate-field-induced breakdown, and 4) parasitic pnpn diode latchup.
Operation and construction of each of the four main types of ESD protection circuits have been described in various publications, such as the textbook "SILICON PROCESSING FOR THE VLSI ERA"--VOLUME II, 1990, pp. 442-446 and therefore are not described further herein.
Also, an output ESD protection circuit is described in an article entitled "OUTPUT ESD PROTECTION TECHNIQUES FOR ADVANCED CMOS PROCESSES", C. Duvvury et al., 1988 EOS/ESD SYMPOSIUM PROCEEDINGS, pp. 206-211.
This article describes a buried n+ (BN+) diffusion output device structure for an output ESD protection circuit for advanced CMOS processes (specifically in dynamic random access memories--DRAMs). According to this article, the BN+ devices can be incorporated into both pull-up and pull-down output devices with adequate drive currents and no transconductance degradation. However, as the article points out, there might be a concern about the devices' hot electron reliability due to reduced channel length and possible extra trap centers introduced by the BN+ process.
Though the output circuit mentioned above provides reasonable ESD protection, its possible that inherent problems may not deem this structure as being desirable. The output ESD protection circuit of the present invention allows ESD protection equal to or greater than the voltage range of +8000/-2000 V for the HBM response (the Mil. Std. human body model [HBM] test model) as well as protection equal to or greater than the voltage range of +900/-700 V for the MM EIAJ response (the EIAJ machine model [MM] test model) due to its' unique and yet simplistic fabrication layout.
All publications cited herein are hereby incorporated by reference.